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Universal serial bus full-speed device interface (USB)
Table 154. Isochronous memory buffers usage
RM0008
Endpoint
Type
DTOG bit
value
0
Packet buffer used by the
USB peripheral
ADDRn_TX_0 / COUNTn_TX_0
buffer description table
locations.
Packet buffer used by the
application software
ADDRn_TX_1 / COUNTn_TX_1
buffer description table
locations.
IN
ADDRn_TX_1 / COUNTn_TX_1
ADDRn_TX_0 / COUNTn_TX_0
OUT
1
0
1
buffer description table
locations.
ADDRn_RX_0 / COUNTn_RX_0
buffer description table
locations.
ADDRn_RX_1 / COUNTn_RX_1
buffer description table
locations.
buffer description table
locations.
ADDRn_RX_1 / COUNTn_RX_1
buffer description table
locations.
ADDRn_RX_0 / COUNTn_RX_0
buffer description table
locations.
As it happens with double-buffered bulk endpoints, the USB_EPnR registers used to
implement Isochronous endpoints are forced to be used as unidirectional ones. In case it is
required to have Isochronous endpoints enabled both for reception and transmission, two
USB_EPnR registers must be used.
The application software is responsible for the DTOG bit initialization according to the first
buffer to be used; this has to be done considering the special toggle-only property that these
two bits have. At the end of each transaction, the CTR_RX or CTR_TX bit of the addressed
endpoint USB_EPnR register is set, depending on the enabled direction. At the same time,
the affected DTOG bit in the USB_EPnR register is hardware toggled making buffer
swapping completely software independent. STAT bit pair is not affected by transaction
completion; since no flow control is possible for Isochronous transfers due to the lack of
handshake phase, the endpoint remains always ‘11’ (Valid). CRC errors or buffer-overrun
conditions occurring during Isochronous OUT transfers are anyway considered as correct
transactions and they always trigger an CTR_RX event. However, CRC errors will anyway
set the ERR bit in the USB_ISTR register to notify the software of the possible data
corruption.
21.4.5
524/995
Suspend/Resume events
The USB standard defines a special peripheral state, called SUSPEND, in which the
average current drawn from the USB bus must not be greater than 500 ? A. This requirement
is of fundamental importance for bus-powered devices, while self-powered devices are not
required to comply to this strict power consumption constraint. In suspend mode, the host
PC sends the notification to not send any traffic on the USB bus for more than 3mS: since a
SOF packet must be sent every mS during normal operations, the USB peripheral detects
the lack of 3 consecutive SOF packets as a suspend request from the host PC and set the
SUSP bit to ‘1’ in USB_ISTR register, causing an interrupt if enabled. Once the device is
suspended, its normal operation can be restored by a so called RESUME sequence, which
can be started from the host PC or directly from the peripheral itself, but it is always
terminated by the host PC. The suspended USB peripheral must be anyway able to detect a
RESET sequence, reacting to this event as a normal USB reset event.
Doc ID 13902 Rev 9
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